Programmable integrated circuits (ICs) may be programmed by a user to perform specified logic functions. One type of programmable logic device, known as a field programmable gate array (FPGA), is very popular because of a superior combination of capacity, flexibility, time-to-market, and cost. Programmable ICs provide the flexible hardware solutions ideal for high performance parallel computing required for advanced digital communications and video applications. For many complex applications, there has been a recent trend to implement a portion of the design in software and a portion of the design in programmable logic. Many manufacturers, such as Xilinx, Inc., include embedded processor systems in a number of programmable integrated circuits. These embedded processor systems offer an ideal combination to meet both the software and hardware programmable needs. Embedded processor systems often include operating memory, software instruction storage, input/output, and other components of a computer system. These systems are referred to as system on chip (SOC) solutions. In these systems, designers may implement complex functions in programmable logic to increase efficiency and throughput. This architectural combination gives an advantageous mix of serial and parallel processing, flexibility, and scalability, thereby enabling a more optimized system partitioning—especially in the areas of intelligent video, digital communications, machine systems, and medical devices.
Given the variety of options available to designers, a design may include several portions split between software and programmable logic of one or more integrated circuits. However, implementing a suitable arrangement for communication between different portions poses a challenge to designers. Data bus architectures provide a convenient method to communicate data between the various portions of a system. In a data bus architecture, one or more communication channels are shared by multiple devices. Communication on each channel is coordinated so that only one device communicates data on the channel at a given time. Data busses typically implement buffering of data. Buffering decouples the communication between devices from the processing of data. Through buffering, several data packets can be transmitted in a burst mode and buffered until the processing circuit is available.
Data busses may be implemented with a number of different data bus architectures such as the Peripheral Component Interconnect (PCI) and the Advanced Microcontroller Bus Architecture (AMBA) bus architectures. Designers typically implement interface circuits to communicate data to and from the data bus in a manner compliant with the chosen data bus protocol. However, because different cores and processors may communicate in different bit formats, implementation of interface circuitry can be challenging. The complexity of the interface circuitry may be further compounded if the data bus is to perform advanced communication functions not included in the base specification of the chosen data bus protocol.
The disclosed embodiments may address one or more of the above issues.